Method of evaluating the exposure property of data to wafer

ABSTRACT

A method of evaluating of evaluating of the exposure property of data to wafer in which errors of the production of photomask and the formation of patterns caused by defocus in the transfer of data to wafer are considered. Accordingly, errors of the production of photomask and deformation of patterns caused by defocus can be evaluated in the stage of design data. Oversize processing and undersize processing are given to pattern data of the object of process by figure operation for the whole pattern data within errors of the production of photomask according to the specification thereof, and simulation is used as a reference to original pattern data of the object of process, the oversize data in which oversize processing is given to the pattern data and the undersize data in which undersize processing is given to the pattern data, in which the wafer exposure simulation is carried out under the condition of zero focus, or under the each exposure condition of zero focus, a given value minus defocus or a given value plus defocus. The exposure property of data to wafer is evaluated from the results of the wafer exposure simulation.

FIELD OF THE INVENTION

[0001] The present invention relates to the proving and the evaluationtechnique of the exposure property of design data to wafer in theproduction of semiconductor device, and particularly to the proving andevaluating technique of the exposure property of design data to wafer bymeans of the technique of the wafer exposure simulation in the processof miniaturization semiconductor.

BACKGROUND OF THE INVENTION

[0002] In recent years, the progress in high density of circuit andminiaturization of semiconductor device has been made in the productionof semiconductor device. Photomask (it is also called “reticle”) is usedand figures having the length shorter than exposure wavelength ofaligner used in the production of semiconductor have been written onwafer by the exposure of to wafer since the latter half of 1990's.

[0003] In this case, a difference between a pattern formed on photomaskand pattern formed on a semiconductor wafer is generated by thediffraction phenomena of light. For example, patterns of design datashown in FIG. 3(a) become patterns on wafer as shown in FIG. 3(b).

[0004] Namely, the pattern formed on a semiconductor wafer is differentfrom design data by the diffraction phenomena of light and so distorted.

[0005] This is called generally the optical proximity effect.

[0006] In order to change the pattern formed on a semiconductor waferinto the objective shape considering the distortion of pattern formed ona wafer by the optical proximity effect, photomask having correctedpattern different from design data is produced by adding correction todesign data so as to change shapes of patterns on a photomask intoshapes different from design data. The technique of forming the patternadapted to objective design data on a wafer using the

[0007] An example of application of the technique of optical proximitycorrection is shown in FIG. 9.

[0008] In FIG. 9, FIG. 9(a 2), FIG. 9(b 2), FIG. 9(c 2) and FIG. 9(d 2)show the shapes of patterns in case of patterns being formed on a waferusing pattern data shown in FIG. 9(a 1), FIG. 9(b 1), FIG. 9(c 1) andFIG. 9(d 1), respectively.

[0009] Pattern data shown in FIG. 9(a 1) are design data, whereinpatterns formed on a wafer corresponding to patterns 910 come intopatterns having either thin width or short length of length on theoptical proximity effect.

[0010]FIG. 9(b 1) shows data in which OPC is applied to design data(FIG. 9(a 1)).

[0011] In this case, numeral 920 designates OPC patterns, wherein it isassumed that there is not defocus in the wafer exposure or the exposureof data of wafer.

[0012] As s result, patterns formed on wafer corresponding to patterns910 come into patterns 912 shown in FIG. 9(b 2) so that patterns 912approach the shape of patterns of the objective design data as comparedwith patterns shown in FIG. 9(a 2).

[0013]FIG. 9(c 1) shows patterns of data in which OPC 920 is applied todesign data 910 in the same manner as a case shown in FIG. 9(b 1).However, when there is defocus in the wafer exposure, patterns formed ona wafer are deformed, for example, into patterns shown in FIG. 9(c 2).

[0014] In the wafer exposure, considering flatness of wafer and thethickness of resist, there can be defocus of about 300 nm ordinarily.

[0015] Accordingly, OPC technique in which supplementary patterns forincreasing the defocus latitude is applied to design data is alsoapplied as a part of OPC technique for the purpose of the correction ofshape.

[0016] For example, as shown in FIG. 9(d 1), OPC patterns 920 andsupplementary patterns 930 (it is also called assist bars or merely OPCpatterns) for increasing the defocus latitude are applied to design data910 so that the defocus latitude can be increased.

[0017] In this case, even if there is defocus, patterns formed on awafer come into shapes approaching patterns of design patterns (patterns910 shown in FIG. 9(a 1)) in the same manner as in the case of defocusshown in FIG. 9(b 2).

[0018] Namely, according to the use of OPC pattern 930 for theimprovement of defocus latitude shown in FIG. 9(d 1), patterns 914formed on a wafer have the shape as shown in FIG. 9(d 2), even if thereis defocus in the exposure of data to wafer so that the deformation ofpattern caused by the diffraction of light is corrected as compared withthe case shown in FIG. 9(c 2). As a result, the defocus latitude isimproved.

[0019] Accordingly, the improvement of the yield of products in theproduction of semiconductor can be expected.

[0020] As mentioned hereinbefore, a difference between patterns indesign data and shapes of patterns formed on a wafer is generated on theoptical proximity effect in the process of miniaturization ofsemiconductor. Therefore, in recent years, the wafer exposure simulationis employed as the effective means for the evaluation of design data,namely the evaluation of data to which OPC has been applied.

[0021] Referring to FIG. 10, a conventional method of evaluating patterndata by the wafer exposure simulation is explained.

[0022] In FIG. 10, S210 to S260 designate steps of process.

[0023] First, the wafer exposure simulation is mentioned.

[0024] The wafer exposure simulation is done by means of device 10provided with software for simulating shapes of patterns formed on awafer on the basis of patterns 21 of design data as shown in FIG. 11(the device is called wafer exposure simulator), wherein the waferexposure simulator is usually provided with a display and input andoutput terminals.

[0025] The wafer exposure simulation is ordinarily comprised of twosteps of optical simulation (it is also called optical model simulation)and resist-simulation (the resist-simulation is also called developmentsimulation, and one of process model simulations). Further, there isalso a case where the wafer exposure simulation is comprised of threessteps of optical model simulation, resist-simulation and etching processsimulation (the etching process is one of process model simulations).

[0026] In the optical simulation, there is condition of image formationwhich is determined exclusively by wavelength of source, number ofapertures of source (NA), and σ (σ indicates coherency and is alsodesignated by “sigma”). And further aberration and vibration of alignerare considered selectively for optical simulation in the opticalsimulation.

[0027] In the resist-simulation, simulation of development process(resist process) is carried out on the basis of the result determinedexclusively by optical simulation. However, since the number ofparameters is too many, calibrating test pattern and process modelobtained by writing test patterns on a wafer by the exposure of data towafer into measuring the length of the written patterns in simulationmodel is employed.

[0028] Simulation of etching process can be carried out in the samemanner as in simulation of development process (resist process).Therefore, the simulation of etching process can be omitted undercertain circumstances.

[0029] First, test mask 280 is formed on the basis of test pattern data270 (S271) at S272. Then, simulation model B (designated by numeral 290at S280) is formed through the transfer of pattern data to wafer or theexposure of pattern data to wafer through test mask 280 (S273) andmeasurement (S274) of the length of the written pattern on wafer by thewafer exposure.

[0030] Zero defocus is ordinarily assumed for wafer.

[0031] The wafer exposure simulation is carried out using the formedsimulation model B (290) and data with OPC in which OPC is applied todesign data designed to the circuit of semiconductor device as patterndata 210 of object of process 210, by means of the wafer exposuresimulator 250, so that shapes of patterns formed on a wafer areevaluated and proved.

[0032] Simulation model B (290 at S280) is used as reference to patterndata 210 of object of process. The wafer exposure simulation is carriedout at a given defocus (usually zero defocus), by which shapes ofpatterns formed on a wafer are evaluated.

[0033] In this case, simulation model B 290 is comprised of a group ofdimension data obtained by writing patterns on a wafer by the exposureof data to wafer through test mask 280 which is photomask for testproduced on the basis of test pattern data 270 under condition of thewafer exposure with a given defocus (usually zero defocus), measuringdimensions of given transferred patterns to wafer and relating dimensiondata of test pattern data 270, dimension data of test mask 280 anddimension data of patterns on wafer at the correspondent positions witheach other for the respective conditions of the wafer exposure.

[0034] Contents to be evaluated here are evaluations of shapes ofpatterns formed on a wafer. Differentials 23 a, 23 b between patterns 21of data to be processed and shapes of patterns 23 formed on a wafer onthe effect of simulation are measured, as shown in block 23 of FIG. 11.In case of the differentials being larger than prescribed value,correction is made in the step of design.

[0035] The exposure property of data to wafer evaluated made accordingto conventional simulation is made using ideal design patterns andassuming that there is no error in the production of photomask and thatideal zero defocus is set in condition of the wafer exposure.

[0036] Therefore, errors in the production of photomask and deformationof patterns caused by defocus in the wafer exposure could not beevaluated from the wafer exposure simulation.

[0037] Conventional method of evaluation of the exposure property ofdata to wafer was enough until dimensions of patterns formed on a waferare more than about ⅔ of exposure wavelength. However, whenminiaturization progresses further, errors in the production ofphotomask and deformation of patterns caused by defocus become serious.

[0038] With high density of circuit and miniaturization of semiconductordevice progressing in recent years, in the evaluation of the exposureproperty of data to wafer with conventional simulation, there was aproblem that errors in the production of photomask and deformation ofpatterns caused by defocus in the exposure of data to wafer cannot beevaluated by the wafer exposure simulation because ideal design patternsare used assuming that produced photomask has no error in the productionof photomask and that ideal zero defocus is set in the condition ofwafer exposure.

[0039] Corresponding to the above-mentioned problem, it is an object ofthe present invention to provide a method of evaluating the exposureproperty of data to wafer in which errors in the production of photomaskand deformation of patterns caused by defocus in the exposure of data towafer are considered.

[0040] Accordingly, the present invention aims at evaluating errors inthe production of photomask and deformation of patterns cased by defocusin the exposure of data to wafer in the stage of design data.

SUMMARY OF THE INVENTION

[0041] A method of evaluating the exposure property of data to wafer ofthe present invention is a method in which pattern data for theproduction of photomask such as design data designed to the circuit ofsemiconductor device and data in which OPC is applied to design data areused as pattern data of the object of process and the exposure propertyof data to wafer in case of the production of photomask of the object ofprocess is evaluated in the stage of data, without producing photomaskfrom pattern data of the object of process, wherein the method comprisesthe steps: giving oversize processing and undersize processing topattern data of the object of process by the figure operation for allpattern data within a range of errors of the production in thespecification of production of photomask; carrying out the waferexposure simulation using a simulation model provided in advance as areference to original pattern data of the object of process, oversizedata in which oversize processing is given to the pattern data andundersize data in which undersize processing is given to the patterndata under conditions of the wafer exposure of zero defocus or under therespective conditions of wafer exposure of zero defocus, a given valueminus defocus and a given value plus defocus and; evaluating theexposure property of data to wafer from the results of the waferexposure simulation, and wherein the simulation model is comprised of agroup of dimension data obtained by using test mask being photomask fortest produced on the basis of test pattern data, carrying out theexposure of data to wafer under the conditions of zero defocus, or underthe respective conditions of zero defocus, a given value minus defocusand a given value plus defocus, measuring dimensions of the patternstransferred to wafer and relating dimension data of test pattern data,dimension data of patterns on photomask and dimension data of patternson wafer at the correspondent positions with each other for therespective conditions of the wafer exposure.

[0042] Further, a method of evaluating the exposure property of data towafer of the present invention is a method in which pattern data for theproduction of photomask such as design data designed to the circuit ofsemiconductor device and data in which OPC is applied to design data areused as pattern data of the object of process and the exposure propertyof data to wafer in case of the production of photomask of the object ofprocess is evaluated in the stage of data, without producing photomaskfrom pattern data of the object of process, wherein the method comprisesthe steps of: carrying the exposure of data to wafer using simulationmodel provided in advance as a reference to pattern data of the objectof process under the respective conditions of zero defocus, a givenvalue minus defocus and a given value plus defocus and; evaluating theexposure property of data to wafer from the results of the wafer, andwherein the simulation model is comprised of a group of dimension dataobtained by using test mask of photomask for test produced on the basisof test pattern data, carrying out the exposure of data to wafer underthe respective conditions of the wafer exposure of zero defocus, a givenvalue minus defocus and a given value defocus, measuring dimensions ofthe patterns transferred to wafer and relating dimension data of testpattern data, dimension data of patterns on photomask and dimension dataof patterns on wafer at the corresponding portions with each other forthe respective conditions of the wafer exposure.

[0043] In the above-mentioned method of evaluating the exposure propertyof data to wafer, pattern data of the object of process arecharacterized by pattern data in which OPC is applied to design data.

[0044] In this case, design data are data of after layout designdesigned to circuit of semiconductor device has completed.

[0045] Accordingly, a method of evaluating the exposure property of datato wafer of the present invention enables the provision of a method ofevaluating the exposure property of data to wafer in which errors of theproduction of photomask and the deformation of patterns caused bydefocus in the exposure of data to wafer are considered.

[0046] Accordingly, evaluating the errors of the production of photomaskand the deformation caused by defocus in the exposure data to wafer areconsidered is made possible.

[0047] Particularly, oversize processing and undersize processing aregiven to pattern data of the object of process by figure operation forthe whole pattern data within errors of the production of photomask inthe specification of production of photomask, and the wafer exposuresimulation is carried out using the simulation model as a reference tooriginal pattern data of the object of process, the oversize data inwhich oversize processing is given to the pattern data and the undersizedata in which undersize processing is given to the pattern data underthe condition of a desired wafer exposure condition so that the exposureproperty of data to wafer can be evaluated. Accordingly, the degree ofdeformation caused by errors of the production of photomask can beproved by which the evaluation of the exposure property of data to waferbased on the specification of production of photomask is made possible.

[0048] Further, the specification of production of photomask can be setsuitably.

[0049] Further, simulation model is obtained by carrying the exposure ofdata to wafer through the test mask produced on the basis of testpattern data under the respective conditions of the exposure of data towafer under zero defocus, a given minus defocus and a given plusdefocus, measuring dimensions of given patterns transferred to wafer aremeasured and relating dimension data of test pattern data, dimensiondata of patterns on photomask and dimension data of patterns on wafer atcorrespondent portions with each other for the respective conditions ofthe wafer exposure to obtain a group of dimension data. The waferexposure simulation is carried out using the simulation model comprisedof the group of dimension data as a reference under the respectiveconditions of the wafer exposure of zero focus, a given minus defocusand a given plus defocus by which the exposure property of data to waferis evaluated. Accordingly, defocus latitude in the process of productionof wafer can be proved.

[0050] Namely, the degree of deformation caused by errors of theproduction of photomask and the defocus latitude can be proved so thatfeed back of the degree of deformation caused by errors of theproduction of photomask and the defocus latitude to design is madepossible from the viewpoint of accuracy of the production or the load ofproduction of photomask or the yield of wafer prior to the production ofphotomask.

[0051] Further, pattern data of the object of process is effective incase of OPC being applied to design data.

BRIEF DESCRIPTION OF THE DRAWINGS

[0052]FIG. 1 is a flow diagram showing one example of mode of a methodof evaluating of the exposure property of data to wafer of the presentinvention.

[0053]FIG. 2 is a table for illustrating simulation model.

[0054]FIG. 3 is an explanatory drawing showing pattern data used andresults of the wafer exposure simulation.

[0055]FIG. 4 is an explanatory drawing showing pattern data used andresults of the wafer exposure simulation.

[0056]FIG. 5 is an explanatory drawing showing pattern data used andresults of the wafer exposure simulation.

[0057]FIG. 6 is an explanatory drawing showing pattern data used andresults of the wafer exposure simulation.

[0058]FIG. 7 is an explanatory drawing showing pattern data used andresults of the wafer exposure simulation.

[0059]FIG. 8 is an explanatory drawing showing pattern data used andresults of the wafer exposure simulation.

[0060]FIG. 9 is an explanatory drawing of OPC.

[0061]FIG. 10 is a flow diagram of a conventional method of evaluatingthe exposure property of data to wafer.

[0062]FIG. 11 is an explanatory drawing of the wafer exposure simulator.

[0063]FIG. 12 is an explanatory drawing of simulation model.

PREFERRED EMBODIMENT OF THE INVENTION

[0064] Referring to drawings, an example of mode for carrying out theinvention is explained.

[0065]FIG. 1 is a flow diagram showing one example of mode of a methodof evaluating of the exposure property of data to wafer of the presentinvention. FIG. 2 is a table for illustrating simulation model.

[0066] In FIG. 1, numeral 100 designates design data; numeral 110designates pattern data of the object of process; numeral 120 designatesthe specification of photomask; numeral 130 designates oversize data;numeral 140 designates undersize data; numeral 150 designates the waferexposure simulator; numeral 160 designates results of simulation;numeral 170 designates test pattern data; numeral 180 designates a testmask and; numeral 190 designates simulation model A.

[0067] In FIG. 1, S100 to S180 show steps of process.

[0068] Referring to FIG. 1, mode for carrying out a method of evaluatingthe exposure property of data to wafer of the present invention isexplained.

[0069] This example is a method of evaluating exposure property of datato wafer in which pattern data for the production of photomask such asdesign data 100 designed to circuit of semiconductor device and data inwhich OPC is applied to design data 100 is used pattern data 110 of theobject of process and the exposure property of data to wafer isevaluated in case of a photomask of the object of process being producedin the stage of data without producing photomask from pattern data 110of the object of process, wherein oversize processing and undersizeprocessing are given to the whole of pattern data 110 of the object ofprocess within a range of errors in the specification of production ofphotomask by figure operation; the wafer exposure simulation is carriedout using simulation model A 190 provided in advance as a reference tooriginal data 110 of the object of process, oversize data 130 in whichoversize processing is given to the pattern data and undersize data 140in which undersize processing is given to the pattern data under therespective conditions of exposure of wafer to wafer of zero defocus, agiven value minus defocus and a given value plus defocus and; theexposure property of data to wafer is evaluated from the results of thewafer exposure simulation.

[0070] The simulation model A 190 used here is comprised of a group ofdimension data obtained by carrying out the exposure of data to waferthrough test mask 180 which is photomask for test produced on the basisof test pattern data 170 under the respective conditions of the waferexposure with zero focus, a given value minus defocus and a given valueplus defocus focus, measuring dimensions of given transferred patternsto wafer and relating dimension data of patterns of test pattern data,dimension data of patterns on patterns on photomask and dimension dataof patterns on wafer at the correspondent positions with each other forthe respective conditions of the exposure of data to wafer.

[0071] First, pattern data 110 of the object of process is provided(S110).

[0072] Design data 100 designed to circuit of semiconductor device, datain which OPC is applied to design data 100 and pattern data in whichsome processing is given to the design data 100 can be used as patterndata 110 of the object of process. However, in this case, pattern dataof the object of process is assumed to be pattern data in which OPC isapplied to design data 100 (SI 00) to explain it simply.

[0073] Then, oversize processing and undersize processing are given tothe whole of pattern data 110 of the object of process within a range oferrors in the specification of production of photomask by figureoperation (S131, S141), by which original pattern data 110 of the objectof process, oversize data 130 in which oversize processing is given tothe pattern data (S132) and undersize data 140 in which undersizeprocessing is given to the pattern data (S142) a re obtained.

[0074] On the other side, test mask 180 for test (S172) is produced onthe basis of test pattern data 170 (S171). The exposure of data to wafer(S173) is carried out under the respective conditions of wafer exposureof zero defocus, a given value minus defocus and a given value plusfocus. Further, dimension data of patterns of given transferred patternsare measured (S174) and dimension data of patterns of test pattern data,patterns on photomask and patterns on wafer at the correspondentpositions are related with each other for the respective conditions ofthe wafer exposure so that a group of dimension data is provided assimulation model A190 (S180).

[0075] For example, in the exposure of data to wafer (S173), light isapplied to wafer with keeping conditions of the exposure to wafer underconditions of zero defocus as well as +300 nm defocus and −300 nmdefocus. Results of the measurement of dimensions of patterns areobtained as + defocus data and − defocus data.

[0076] In this case, conditions for carrying out some general waferexposure simulation (for example, by means of Calibre ORC manufacturedby Mentor Graphics Corporation) is set.

[0077] Test mask 180 (S172) is produced on the basis of sourcewavelength (for example, 248 nm), number of aperture of source (NA: forexample 0.7), source filter (for example, out: 0.7/in: 0.5) and usingtest pattern data 170 (S171). Light is applied to wafer by means of awafer aligner (S173) and measurement of dimensions of the patternsformed on wafer is made (S174).

[0078] Examples of part of the test pattern data 170 are illustrated inFIG. 12(a), wherein numeral 1101 to 1104 designate ID of the testpattern data 170.

[0079] There are various test pattern data including line & spaceprovided from a maker of simulator as the test pattern data shown inFIG. 1.

[0080] Test masks (designated by numeral 180 in FIG. 1) are produced onthe basis of the test pattern data (designated by numeral 170 in FIG.1).

[0081]FIG. 12(b) shows shapes of patterns of photomasks, wherein numeral1105 to 1108 designates shapes of patterns of photomasks correspondingto test pattern data with ID 1101 to 1104, respectively.

[0082]FIG. 12(c) shows patterns transferred on wafer through thephotomasks, wherein numeral 1109 to 1112 designate patterns transferredon wafer corresponding to test pattern data with ID 1101 to 1104.

[0083] In this case, a difference between dimensions of test masks 180and dimensions of test pattern data 170 is generated.

[0084] When conventional simulation model B 290 (S280) shown in FIG. 10is produced, data on dimensions of pattern of pattern data, dimensionsof pattern formed on photomask, and dimensions of pattern formed onwafer are made into a table as shown in FIG. 12(d). The data shown inthe table shown in FIG. 12(d) are provided as simulation model B 290. Onthe other hand, as mentioned hereinbefore, simulation model A 190 (S180)used in the present example is comprised of a group of dimension dataobtained by transferring patterns on wafer (S173) through test mask 180(S172) which is photomask 180 for test produced on the basis of testpattern data 170 (S171) under the respective conditions of the waferexposure with zero focus, a given value minus defocus and a given valueplus defocus, measuring dimensions of a given transferred patterns(S174) and relating dimension data of patterns of test pattern data,patterns on photomask and patterns on wafer at the correspondentpositions with each other for the respective conditions of the exposureto wafer. A table as shown in FIG. 2 is provided as simulation model.

[0085] Generally, if tables as shown in FIG. 2 and FIG. 12(d) are setup, simulator model used as a reference by simulator can beautomatically generated by additional function of simulator.

[0086] In this case, tables shown in FIG. 2 and FIG. 12(d) are alsocalled simulation model.

[0087] The accuracy of the production of photomask is recorded in thespecification 120 of photomask, as +/−20 nm against dimensions ofdesign, for example.

[0088] Photomask is produced and evaluated on the basis of accuracy ofdimensions of production, wherein actual dimensions of photomask can bechanged within the accuracy of dimensions of production.

[0089] Accordingly, generally, in case of accuracy of dimensions ofproduction being +/−20 nm, oversize data 130 is formed by makingoversize pattern data 110 of the object of process by 20 nm by oversizeprocessing 131 and undersize data 140 is formed by making undersizepattern data 110 of the object of process by 20 nm by undersizeprocessing 141.

[0090] Then, the wafer exposure simulation of pattern data 110 of theobject of process, oversize data 130 and undersize data 140 are carriedout (S150) using the wafer exposure simulator (designated by numeral 10in FIG. 11).

[0091] When simulation is carried out with the pattern data 110 of theobject of process, oversize data 130 and undersize data 140, simulationsarea carried out using each pattern data with the above-mentioned zerofocus data, + defocus data and − defocus data, respectively, Namely,nine simulations of three pattern data by focus data are carried out.

[0092] Of course, since there is a case that both sides of plus andminus are not defined on the zero standard as the specification ofproduction of photomask defined on only + side of zero standard or as arange of defocus defined on only − side of a range of defocus of zerostandard, generally, simulations amount to four sorts through ninesorts.

[0093] Referring to FIG. 3 through FIG. 8, examples of shapes ofpatterns formed on wafer obtained by such various wafer exposuresimulations are mentioned.

[0094]FIG. 3(a), FIG. 4(a), FIG. 5(a), FIG. 6(a), FIG. 7(a) and FIG.8(a) show pattern data, respectively. FIG. 3(b), FIG. 4(b), FIG. 5(b),FIG. 6(b), FIG. 7(b) and FIG. 8(b) show shapes patterns obtained by thewafer exposure simulation in case of pattern data shown in FIG. 3(a),FIG. 4(a), FIG. 5(a), FIG. 6(a), FIG. 7(a) and FIG. 8(a), respectively.

[0095] FIGS. 3 thorough 7 show a case that patterns are transferred on awafer in zero focus. FIG. 8 shows a case that patterns are transferredon a wafer in defocus.

[0096]FIG. 3 shows simulation of general optical proximity effect.

[0097] Rounded patterns 311 shown in FIG. 3(b) are obtained to patterns310 of the object of process.

[0098]FIG. 4 shows an example of simulating the influence of errors ofthe production of photomask on the plus side in the specification ofproduction of photomask, wherein FIG. 4(a) shows patters 410 in whichpattern data 310A of the object of process (area bounded by the dottedline) is oversized as shown by the shadowed portion and FIG. 4(b) showspatterns 411 deformed by the influence of the plus errors of theproduction of photomask. In FIG. 4(b), numeral 311A designates roundedpatterns obtained to patterns 310A of the object of process.

[0099] Even if errors of the production of photomask are uniform, thevalues of deformations depend on whether patterns are arranged sparselyor densely. Therefore, there are portions in which the values ofdeformation are remarkably increased and portions in which the values ofdeformations are kept at small values so that portions with large valuesof deformation can be detected.

[0100] In the same manner, FIG. 5(a) shows patterns 511 in which patterndata 310A of the object of process (area bounded by the dotted line) isundersized as shown by the shadowed portion and FIG. 5(b) shows resultsof simulating the patterns 510.

[0101] In case of undersize processing, deformations in which adjacentpatterns are connected with each other are not generated. However, thereis a case that patterns cannot be resolved.

[0102]FIGS. 6 through 8 show simulation made under the consideration ofthe defocus latitude.

[0103]FIG. 6(a) shows a case that assist bar OPC is applied to patternsof the object of process wherein pattern 610 of the object of processand OPC patterns 620 are arranged and FIG. 6(b) shows shapes of patterns611 formed on wafer corresponding to patterns 610.

[0104]FIG. 7(a) shows a case that assist bar OPC is applied, whereinpatterns 710 of the object of process and the same OPC patterns 720 arearranged in the same manner as patterns shown in FIG. 6(a) and a part ofthe OPC patterns 720 is cut from some reason.

[0105] Since OPC patterns 720 are OPC for increasing the defocuslatitude, the influence of OPC patterns hardly appears in the state ofzero focus. Therefore, shapes of patterns formed on wafer become almostthe same in a case shown in FIG. 6(b) and a case shown in FIG. 7(b).

[0106]FIG. 8 shows result of simulation (FIG. 8(b)) in which theexposure of data of to wafer is made using data of the object of processshown in FIG. 7(a) and under the condition of defocus. Results of theexposure of data to wafer shown in FIG. 8(b) differs from results ofsimulation shown in FIG. 7(b), wherein thinned part 712A is generated atportion corresponding to the cut of OPC pattern 720 in patterns 712 onpatterns 712 on wafer corresponding to patterns 710 of pattern data ofthe object of process.

[0107] The cut of a part of OPC pattern can be detected by detecting thethinned part 712A.

[0108] In such a way, according to the present simulation, shapes ofpatterns formed on a wafer can be obtained under various conditions andportion of bad condition can be detected for data of the object ofprocess from shapes of the obtained patterns on a wafer.

[0109] The results can be fed back for reformation or correction ofpattern data of the object of process. Accordingly, a method ofevaluating the exposure of data to wafer in which deformation ofpatterns caused by errors of the production of photomask and defocus inthe exposure of data to wafer becomes possible.

[0110] Namely, it is possible to evaluate errors of the production ofphotomask and deformation caused by defocus in the exposure of data towafer in the stage of pattern data.

[0111] As mentioned hereinbefore, the present invention enables theproduction of a method of evaluating the exposure of data to wafer inwhich errors of the production of photomask and deformation of patternscaused by defocus in the exposure of data to wafer are considered.According to the present invention, it is made possible to evaluateerrors of the production of photomask and deformation caused by defocusin the exposure of data to wafer in the stage of design data.

[0112] Particularly, according to the present invention, it is madepossible to deal with high density of circuit and the miniaturization ofsemiconductor device.

What is claimed is:
 1. A method of evaluating the exposure property ofdata to wafer of the present invention in which pattern data for theproduction of photomask such as design data designed to the circuit ofsemiconductor device and data in which OPC is applied to design data areused as pattern data of the object of process and the exposure propertyof data to wafer in case of the production of photomask of the object ofprocess is evaluated in the stage of data, without producing photomaskfrom pattern data of the object of process, wherein the method comprisesthe steps: giving oversize processing and undersize processing topattern data of the object of process by the figure operation for allpattern data within a range of errors of the production in thespecification of production of photomask; carrying out the waferexposure simulation using a simulation model provided in advance as areference to original pattern data of the object of process, oversizedata in which oversize processing is given to the pattern data andundersize data in which undersize processing is given to the patterndata under conditions of the wafer exposure of zero defocus or under therespective conditions of wafer exposure of zero defocus, a given valueminus defocus and a given value plus defocus and; evaluating theexposure property of data to wafer from the results of the waferexposure simulation, and wherein the simulation model is comprised of agroup of dimension data obtained by using test mask being photomask fortest produced on the basis of test pattern data, carrying out theexposure of data to wafer under the conditions of zero defocus, or underthe respective conditions of zero defocus, a given value minus defocusand a given value plus defocus, measuring dimensions of the patternstransferred to wafer and by relating dimension data on patterns testpattern data, dimension data on photomask and dimension data on patternson wafer at the correspondent positions with each other for therespective conditions of the wafer exposure.
 2. A method of evaluatingthe exposure property of data to wafer of the present invention in whichpattern data for the production of photomask such as design datadesigned to the circuit of semiconductor device and data in which OPC isapplied to design data are used as pattern data of the object of processand the exposure property of data to wafer in case of the production ofphotomask of the object of process is evaluated in the stage of data,without producing photomask from pattern data of the object of process,wherein the method comprises the steps of: carrying the exposure of datato wafer using simulation model provided in advance as a reference topattern data of the object of process under the respective conditions ofzero defocus, a given value minus defocus and a given value plus defocusand; evaluating the exposure property of data to wafer from the resultsof the wafer, and wherein the simulation model is comprised of a groupof dimension data obtained by using test mask of photomask for testproduced on the basis of test pattern data, carrying out the exposure ofdata to wafer under the respective conditions of the wafer exposure ofzero defocus, a given value minus defocus and a given value defocus,measuring dimensions of the patterns transferred to wafer and relatingdimension data of test pattern data, dimension data of patterns onphotomask and dimension data on wafer at the corresponding portions forthe respective conditions of the wafer exposure.
 3. A method ofevaluating the exposure property of data to wafer as claimed in claim 1or 2, wherein pattern data of the object of process is pattern data inwhich OPC is applied to design data.